TDA5230 Datasheet, PDF (104/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
TSILENA = 16d, TSILENB = 6d
RunIn
Incoming Pattern ^{0 0 0 0 0 1 0 1 0 0 0 1 1 1 1 1 0 1 0 0 1 0}
Manchester Coded
TSI Pattern Match
FSYNC
Data into FIFO
01010101011001100101011010101010011001011001
TSIPTB
TSIPTA
5 4 3 2 1 0 151413121110 9 8 7 6 5 4 3 2 1 0
0110011001010110101010
1010010
Figure 49 TSI Mode 16-Bit
8-Bit Mode: As two correlators working simultaneously in parallel of up to
16 chips length each
In the following example, TSI Pattern B matched first and generates a FSYNC. The
lengths of both TSI Patterns are now independently from each other.
TSILENA = 16d, TSILENB = 6d
RunIn
Incoming Pattern
00000101010010
Manchester Coded
TSI Pattern B Match
FSYNC
Data into FIFO
0101010101100110011001011001
TSIPTB
543210
011001
1010010
Figure 50 TSI Mode 8-Bit
8-Bit Gap Mode: As two sequentially working correlators of up to 16 chips
length each
This mode is only used in combination with the TSI GAP Mode!
This mode is used to define a gap between the two patterns which is preset in the
TSIGAP register.To identify exactly the beginning of the Gap it would be helpful on
occasion to place the first CV of the Gap into the TSI Pattern A. In this case, the Gap
length needed for the TSIGAP register must be shortened and the TVWIN length must
be extended (see also Chapter 2.4.13 Frame Synchronization).
Data Sheet
100
Version 4.0, 2007-06-01