TDA5230 Datasheet, PDF (112/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
TVWIN = round(max{((8 + 16 ⋅ CV + 8) ⋅ 1,25), (8 + 16 ⋅ TSIA_CV + 16 ⋅ 1 + 8) ⋅ 1,25})
Dual: ATSIMODE and BTSIMODE: TSI Detection Mode
ADDR: 0x82 and 0xA2
Reset Value: 0x00
Bit R/W Description
7 W TSIGRSYN: TSI Gap Resync Mode (For detailed information, see
ATSIGAP/BTSIGAP register description)
0: OFF
1: PLL reset after TSI Gap
2 W MANCPAJ: Manchester code phase readjustment
0: disabled - Manchester code polarity is defined by the TSI pattern. Use as
default, if TSI 8bit GAP Mode is not used
1: enabled - the code phase readjustment will be done with each “1001” or
“0110” Manchester data change. Use for TSI 8bit GAP Mode
Dual: ATSIGAP and BTSIGAP: TSI GAP
ADDR: 0x85 and 0xA5
Reset Value: 0x00
Bit R/W Description
7:3 W TSIGAP: TSI Gap (T/2 bit resolution)
1Fh: 15 1/2 bit gap
00h: 0 bit gap
TSIGAP is used to lock the PLL after TSI A is found, if the TSI detection
mode 10b is selected.
2:0 W GAPVAL: TSI Gap (T/16 bit resolution)
111b: 7/16 bit gap
000b: 0 bit gap
GAPVAL is used to correct the DCO phase after TSIGAP time, if the
TSIMODE.TSIGRSYN is disabled
Data Sheet
108
Version 4.0, 2007-06-01