TDA5230 Datasheet, PDF (162/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Register Descriptions
Dual: ATSIMODE and BTSIMODE: TSI Detection Mode
ADDR: 0x82 and 0xA2
Reset Value: 0x00
Bit R/W Description
7 W TSIGRSYN: TSI Gap Resync Mode (For detailed information, see
ATSIGAP/BTSIGAP register description)
0: OFF (default)
1: PLL reset after TSI Gap
6:3 W TSIWCA: Wild Cards for Correlator A
2 W MANCPAJ: Manchester Code Phase Readjustment
0: disabled - Manchester code polarity is defined by the TSI pattern.
1: enabled - the code phase readjustment will be done with each “1001” or
“0110” Manchester data change.
1:0 W TSIDETMOD: TSI Detection Mode
00b: 16-Bit Mode - TSI configuration A AND B valid (sequentially), B is valid
if the ATSILENB>0
01b: 8-Bit Mode - TSI configurations A OR B (parallel)
10b: 8-Bit Gap Mode- TSI configurations A AND B with Gap (sequentially
with Gap between TSIA & TSIB)
11b: 8-Bit extended Mode - TSI configurations A OR B (parallel with
matching information), synchronization will be done on full TSI length,
dependent on found TSI A or B, 0 or 1 will be sent as 1st received bit.
Dual: ATSILENA and BTSILENA: TSI A Length
ADDR: 0x83 and 0xA3
Reset Value: 0x00
Bit R/W Description
4:0 W TSI A Length (in chips):
(0x11 up to 0x1F not used)
Min: 00h = 0 Bit; Does only work in 16-Bit Mode: FSYNC will be generated
after Symbol Synchronization. In other Modes the smallest possible value to
generate a FSYNC will be 01h. Be aware that such small values makes it
impossible to find the correct phase of the pattern in the data stream and,
therefore, wrong data and code violations can be generated.
Max: 10h = 16 chips = 8 bits
Data Sheet
158
Version 4.0, 2007-06-01