TDA5230 Datasheet, PDF (96/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
TVWIN CV Window Length
The PLL unlocks if the reference signal is lost for more than the time defined in the
TVWIN register. During the TSI GAP (See TSI GAP Mode) the PLL and the TVWIN are
frozen.
The TVWIN time is the time that DigRX should stay locked without incoming signal
edges detected. The time resolution is T/16.
TVWIN is calculated as follows:
TVWIN = round((8 + 16 ⋅ CV + 8) ⋅ 1,25)
CV is the number of code violations in a block.
This calculation is done by IAF TDA523x Configuration Tool, if the number of CV’s
is entered.
Dual: ACDR0 and BCDR0: Clock recovery P parameters
ADDR: 0x73 and 0x93
Reset Value: 0x00
Bit R/W Description
7:6 W PDSR: Peak Detector slew rate
use 11b
5 W PHDEN(1): Phase detector error (PDE) outer tolerance range
use 1b
4 W PHDEN(0): Phase detector error (PDE) inner tolerance range
use 0b
3:2 W PVAL: P Value
use 01b
1:0 W PSAT: P Value Saturation
use 10b
Dual: ACDR1 and BCDR1: Clock recovery I parameters
ADDR: 0x74 and 0x94
Reset Value: 0x00
Bit R/W Description
7:6 W CORSAT: Correlator output value (Timing extrapolation unit)
use 01b
5:4 W LFSAT: Loop Filter Saturation
use 10b
Data Sheet
92
Version 4.0, 2007-06-01