TDA5230 Datasheet, PDF (82/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
from
FSK-
Demodulator
from
RSSI-
Generator
from
Master-Control-Unit
f_sys
Clock-Generation
T_nom / 16
A
D
Pre
Slicer
EoC
SoC
Peak
Detector
RSSI-Track
RSSI-Clear
CIC
Filter
A/D
Control-Unit
T_nom / 16
unsliced data
Dif
at rate T_nom / 16
to
signal
detection
EOM
Figure 40 AD-Control and Matched-FIlter
AD Converter:
The AD sampling rate division factor ADCDIV is always a multiple of 16 times of the data
rate, and in a range from 96 kHz to 320 kHz. For example for a 2 kb/s data rate the ADC
sampling rate has to be a multiple of 32 kHz, the optimal ADC sampling rate is 320 kHz.
Because of f_SYS and the used clock divider, not all ADC sampling rates are possible.
Therefore, there is an ideal sample rate (e.g. 320 kHz) and finally a real sample rate
(322.576 kHz, note: values slightly higher than 320 kHz are tolerated if calculated by the
IAF Tool). The difference between the ideal and the real sample rate should not be more
than 2%. For better performance, the highest possible ADC sampling rate should be set.
For data rates lower or equal to 1.1kb/s a maximum sample rate of 120 kHz should be
selected.
A data decimation is required to correct the values which are dependent on the factor of
oversampling.
The calculation formulas for ADCDIV / ASKDEC factors:
The following calculations are fully supported by the IAF TDA523x Configuration
Tool!
Data Sheet
78
Version 4.0, 2007-06-01