TDA5230 Datasheet, PDF (101/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
Dual: AWUPAT1 and BWUPAT1: Conf.A Wake Up Detection Pattern1
ADDR: 0x27 and 0x48
Reset Value:0x00
Bit R/W Description
7:0 W WUPAT1: Wake Up Detection Pattern: Bit 15(MSB)...Bit 8 (in Chips)
Dual: AWUBCNT & BWUBCNT: Conf.A Wake Up Bit Count Register
ADDR: 0x28 and 0x49
Reset Value:0x00
Bit R/W Description
6:0 W WUBCNT: Wake Up Bit Count Register
Counter Register to define the maximum counts of chips for Wake Up
detection.
Min: 00h = 0 Chips to count
In “Random Bits” or “Equal Bits” Mode, this will cause a Wake Up
immediately after Symbol Synchronization is found.
In “Pattern Detection” Mode, this will cause no Wake Up found. In
this Mode, there is a required minimum of 11h= 17 Chips= 8.5 Bits
to shift one Pattern through the entire Pattern Detector because
comparison can only be started when at least the comparison
register is fully filled.
Max: 7Fh: 127 Chips to count after Symbol Sync found
Data Sheet
97
Version 4.0, 2007-06-01