TDA5230 Datasheet, PDF (159/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Register Descriptions
Dual: ATVWIN and BTVWIN: CV Window Length
ADDR: 0x77 and 0x97
Reset Value: 0x00
Bit R/W Description
7:0 W TVWIN: CV Window Length
28h: 40/16 bits
FFh: 255/16 bits
The minimal value for the TVWIN Register must be configured to 1 CV=28h
((8 + 16 *CV + 8)*1.25). Note that if the TSIGAP framer mode is used (e.g.
8-bit Gap protocol) the value must be higher and is dependent on other TSI
framer settings.
Dual: AFSKNCO0 and BFSKNCO0: FSK DDS NCO Frequency Offset
ADDR: 0x78 and 0x98
Bit R/W Description
7:0 W NCOINC: FSK NCO Register Bits (7:0) LSB
Reset Value: 0x00
Dual: AFSKNCO1 and BFSKNCO1: FSK DDS NCO Frequency Offset
ADDR: 0x79 and 0x99
Bit R/W Description
7:0 W NCOINC: FSK NCO Register Bits (15:8)
Reset Value: 0x00
Dual: AFSKNCO2 and BFSKNCO2: FSK DDS NCO Frequency Offset
ADDR: 0x7A and 0x9A
Bit R/W Description
7:0 W NCOINC: FSK NCO Register Bits (23:16) MSB
Reset Value: 0x00
Dual: AFSKFILBW0 and BFSKFILBW0: FSK Pre Filter Decimation
ADDR: 0x7B and 0x9B
Bit R/W Description
3:0 W FSKDEC: FSK Pre-Filter Decimation Factor
0001b: ±250 pre-filter bandwidth (recommended)
0011b: ±125 pre-filter bandwidth
0111b: ±62.5 pre-filter bandwidth
1111b: ±31.25 pre-filter bandwidth
Reset Value: 0x00
Data Sheet
155
Version 4.0, 2007-06-01