TDA5230 Datasheet, PDF (103/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
Manchester-
Decoder
Data
Data Clock
Code-Violation CV
Detector
EOM-Detector
EMCV
EMSYLO
EMDATLEN
EOMDTLEN
Data
Data Clock
EOM
Sync
from CR
from Data-Slicer
Chip-Data Clock
Chip-Data
TSI wild card
MRB
Delay-Line 16-bit
Correlator A 16-bit
LRB
LSB
TSI Data-Pattern
MSB LSB
TSI Data-Pattern
MSB
Correlator A
Controller
TSILENA
Frame
Synchronization
Controller
FSync
CorrAMatch
MUX
MRB
Delay-Line 16-bit
Correlator B 16-bit
LRB
LSB
TSI Data-Pattern
MSB LSB
TSI Data-Pattern
MSB
Correlator B
Controller
TSILENB
TSIMODE
TSIGAP
Figure 48 Frame Synchronisation Unit
The two independent correlators can be configured in the TSIMODE register to work in
one of the following four modes:
16-Bit Mode: As a single correlator of up to 32 chips
The length of the TSILENA register has to be set to 16d whenever TSILENB is higher
than 0.
Data Sheet
99
Version 4.0, 2007-06-01