TDA5230 Datasheet, PDF (145/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
SN2: Serial Number Register 2
ADDR: 0x10
Bit R/W Description
7:0 R SN: Serial Number: Bit 23...Bit 16
Register Descriptions
Reset Value: SN
SN3: Serial Number Register 3
ADDR: 0x11
Bit R/W Description
7:0 R SN: Serial Number: Bit 31 (MSB)...Bit 24
Reset Value: SN
RFC: RF Control Register
ADDR: 0x12
Reset Value: 0x00
Bit R/W Description
4 W RFOFF: Switch off RF-path (for RSSI trimming)
0: RF-path enabled
1: RF-path off
3:0 W IFATT: Adjust IF attenuation in 16 steps to trim the gain RFIN --> IF-OUT
0000: 0 dB attenuation
1111: 12 dB attenuation
CLKOUT0: Clock Divider Register 0
ADDR: 0x13
Bit R/W Description
7:0 W CLKOUT0: Clock Out Divider: Bit 7...Bit 0 (LSB)
Min: 0 00 01h = Clock divided by 2
Max: 0 00 00h = Clock divided by (2^20)*2
Reset Value: 0x07
CLKOUT1: Clock Divider Register 1
ADDR: 0x14
Bit R/W Description
7:0 W CLKOUT1: Clock Out Divider: Bit 15...Bit 8
Min: 0 00 01h = Clock divided by 2
Max: 0 00 00h = Clock divided by (2^20)*2
Reset Value: 0x00
Data Sheet
141
Version 4.0, 2007-06-01