TDA5230 Datasheet, PDF (80/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
input data
RUNIN
chip-data available
data available
TSI
TSI
TSI
T₁ T₂
T₃
Figure 39 Data Latency
RUNIN
RUNIN
PLL re-synchronization
RUNIN
T₂ T₂
The synchronization search time T₃ is the time the receiver requires for a search for a
pattern in an incoming data stream. The minimum value of the search time out length is
the consequence of the system latency time T₁ and RUNIN length.
The overall system latency time is calculated in two steps: T₁ is the delay between ADC
input and the filter output (chip data available), and T₂ is the time between the Slicer input
and the Framer output (decoded data available).
T₁ latency time include: (T₁ = 2 2/16 T + 0.5 T)¹⁾
• matched filter computation time
• signal detector delay
T₂ latency time include: (T₂ = 1.5 T to 2.0 T)
• Data Slicer computation time
• Framer computation time. The 0.5 T spread is caused by the internal Framer circuit
quantization behavior.
This means, that for the minimum length of the SYSRCT0, the value 2 2/16 bits plus 0.5
bits, plus the RUNIN length, which is set in the CDR2 register, plus 1.5 bits (to consider
worst case RUNIN patterns) have to be used. To reach all data rate and duty cycle errors
10% of the overall sum must be added.
SYSRCT0 = roundup(((RUNIN + 2,125 + 2) ⋅ 16) ⋅ 1,1)
1) T..nominal duration of one data bit
Data Sheet
76
Version 4.0, 2007-06-01