TDA5230 Datasheet, PDF (132/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
3
Register Descriptions
Register Descriptions
Due to the variety of device functions and protocols, several registers and register bits
have dedicated functions according to the selected operation mode. Modification of
register settings, unless otherwise noted, is only allowed in Sleep and Hold Mode.
Registers that are defined independently for each configuration A and B are marked with
“Dual”. Registers marked with “R” are read only, “W” are write only and “C” are cleared
after read.
Settings for all registers are supported by the IAF TDA523x Configuration Tool!
Table 3
Register Descriptions
Name
Addr. R/W Def. Description
Page
SPIAT
0x00 R 0x00 SPI Address Tracer
135
SPIDT
0x01 R 0x00 SPI Data Tracer
135
CMC0
0x02 W 0x40 Chip Mode Control Register 0
135
CMC1
0x03 W 0x00 Chip Mode Control Register 1
136
IS
0x04 C 0xFF Interrupt Status Register
137
IM
0x05 W 0x00 Interrupt Mask Register
138
RFPLLAC
0x06 R 0x00 RF PLL Actual Channel Register
138
SPMC
0x07 W 0x00 Self Polling Mode Control Register
139
SPMRT
0x08 W 0x01 Self Polling Mode Reference Timer
139
SPMOFFT0
0x09 W 0x01 Self Polling Mode Off Time Register 0 139
SPMOFFT1
0x0A W 0x00 Self Polling Mode Off Time Register 1 140
SPMAP
0x0B W 0x01 Self Polling Mode Active Periods Reg. 140
SPMIP
0x0C W 0x01 Self Polling Mode Idle Periods Register 140
SN0
0x0E R Fuse Serial Number Register 0
140
SN1
0x0F R Fuse Serial Number Register 1
140
SN2
0x10 R Fuse Serial Number Register 2
141
SN3
0x11 R Fuse Serial Number Register 3
141
RFC
0x12 W 0x00 RF Control Register
141
CLKOUT0
0x13 W 0x07 Clock Divider Register 0
141
CLKOUT1
0x14 W 0x00 Clock Divider Register 1
141
CLKOUT2
0x15 W 0x00 Clock Divider Register2
142
Data Sheet
128
Version 4.0, 2007-06-01