TDA5230 Datasheet, PDF (151/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Register Descriptions
Dual: AWUPAT1 and BWUPAT1: Conf. A Wake Up Detection Pattern 1
ADDR: 0x27 and 0x48
Reset Value:0x00
Bit R/W Description
7:0 W WUPAT1: Wake Up Detection Pattern: Bit 15(MSB)...Bit 8 (in chips)
Dual: AWUBCNT and BWUBCNT: Conf. A Wake Up Bit Count Register
ADDR: 0x28 and 0x49
Reset Value:0x00
Bit R/W Description
6:0 W WUBCNT: Wake Up Bit Count Register
Counter Register to define the maximum counts of chips for Wake Up
detection.
Min: 00h = 0 chips to count
In “Random Bits” or “Equal Bits” Mode, this will cause a Wake Up
immediately after Symbol Synchronization is found.
In “Pattern Detection” Mode this will cause no Wake Up found. In this
Mode, a minimum of 11h= 17 Chips= 8 1/2 Bits is needed to shift one
Pattern through the entire Pattern Detector because comparison can
only be started when at least the comparison register is fully filled.
Max: 7Fh: 127 Chips to count after Symbol Sync found
Dual: AMID0-AMID19 and BMID0-BMID19: Conf. A Message ID Register 0
ADDR: 0x29-0x3C and 0x4A-0x5D
Bit R/W Description
7:0 W MID0: Message ID Register
Reset Value:0x00
Dual: AMIDC0 and BMIDC0: Conf. A Message ID Control Register 0
ADDR: 0x3D and 0x5E
Reset Value:0x00
Bit R/W Description
6:0 W SP: MID Scan Start Position
Min: 00h = Comparison starts one Bit after FSYNC
Max: 7F = Comparison starts 128 Bits after FSYNC
Data Sheet
147
Version 4.0, 2007-06-01