TDA5230 Datasheet, PDF (154/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Register Descriptions
Dual: ADCSPLRDIV and BDCSPLRDIV: ADC dividing factor
ADDR: 0x6D and 0x8D
Reset Value: 0x00
Bit R/W Description
7:0 W ADCDIV: ADC Sampling Rate Division Factor.
The ADC sampling rate factor must be calculated together with ASKDEC.
Note that for better performance, the highest possible ADC sampling rate
should be set.
ADCDIV
=
ro
un
d


f--f-_A^--s--_Dy^{---sC--}
–
1
f_ADC
=
[ 96 … 320 k H z ]
Dual: APKBITPOS and BPKBITPOS: RSSI Detector Start-up Delay
ADDR: 0x6E and 0x8E
Reset Value: 0x00
Bit R/W Description
7:0 W RSSI Detector Start-up Delay¹⁾
Min: 00h: 0 bit delay (Start with first bit after FSYNC)
Max: FFh: 255 bits delay
1) Due to filtering and signal computation the latency T₁ and T₂ must be added (see also Chapter 2.4.9.1)
Dual: ADATFILT0 and BDATFILT0: Matched Filter Scaling and Delay
ADDR: 0x6F and 0x8F
Reset Value: 0x00
Bit R/W Description
5:3 W ASKSCA: CIC-filter Input Scaling Factor¹⁾
000b: default
2:0 W ASKDEL: CIC-filter cmb Section delay Factor¹⁾²⁾
110b: default
For better performance from reduced duty and data rate errors set 111b.
1) use default value
2) the CIC filter delay = ASKDEL + 1
Data Sheet
150
Version 4.0, 2007-06-01