TDA5230 Datasheet, PDF (150/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Register Descriptions
Dual: ARFPLL3 and BRFPLL3:Conf. A RF PLL setting, channel 3 (Self Polling
Mode)
ADDR: 0x24 and 0x45
Bit R/W Description
4:2 W RFPLLR3: Channel 3, PLL Divider Factor R¹⁾
000 : R = 8
001 : R = 1
010 : R = 2
011 : R = 3
100 : R = 4
101 : R = 5
110 : R = 6
111 : R = 7
1:0 W RFPLLS3: Channel 3, PLL Divider Factor S¹⁾
00 : S = 1
01 : S = 0
10 : S = -1
11 : S = 0
Reset Value: 0x0A
1) Channels with receive frequencies close to the harmonics of the reference crystal frequency should not be
used in applications.
Dual: AWUC and BWUC: Conf. A Wake up Control Register
ADDR: 0x25 and 0x46
Reset Value:0x00
Bit R/W Description
1:0 W WUCRT: Wake Up Criteria
00b: Pattern Detection
01b: Random Bits
10b: Equal Bits
11b: Wake Up on Symbol Sync, Valid Data Rate; the WUBCNT Register is
not used in this mode.
Dual: AWUPAT0 and BWUPAT0: Conf. A Wake Up Detection Pattern 0
ADDR: 0x26 and 0x47
Reset Value:0x00
Bit R/W Description
7:0 W WUPAT0: Wake Up Detection Pattern: Bit 7...Bit 0(LSB) (in Chips)
Data Sheet
146
Version 4.0, 2007-06-01