TDA5230 Datasheet, PDF (136/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Register Descriptions
Table 3
Register Descriptions
Name
Addr. R/W Def. Description
ACDR0
0x73 W 0x00 Clock recovery P parameters
ACDR1
0x74 W 0x00 Clock recovery I parameters
ACDR2
0x75 W 0x00 Clock recovery RUNIN length
ASYSRCT0
0x76 W 0x00 Synchronization search time out
ATVWIN
0x77 W 0x00 CV Window Length
FSK related register
AFSKNCO0
0x78 W 0x00 FSK DDS NCO Frequency Offset
AFSKNCO1
0x79 W 0x00 FSK DDS NCO Frequency Offset
AFSKNCO2
0x7A W 0x00 FSK DDS NCO Frequency Offset
AFSKFILBW0 0x7B W 0x00 FSK Pre Filter Decimation
AFSKFILBW1 0x7C W 0x00 FSK Pre Filter Scaling
AFSKDEMBW0 0x7D W 0x00 FSK Demodulator Sensitivity
AFSKDEMBW1 0x7E W 0x00 FSK DAM Output Decimation
AFSKDEMBW2 0x7F W 0x00 FSK DAM Output Scaling
ANDTHRES
0x80 W 0x00 FSK Noise Detector Threshold
ANDCONFIG 0x81 W 0x00 FSK Noise Detector configuration
Framer related register
ATSIMODE
0x82 W 0x00 TSI Detection Mode
ATSILENA
0x83 W 0x00 TSI A Length
ATSILENB
0x84 W 0x00 TSI B Length
ATSIGAP
0x85 W 0x00 TSI GAP
ATSIPTA0
0x86 W 0x00 TSI Data Reference Low Byte A
ATSIPTA1
0x87 W 0x00 TSI Data Reference High Byte A
ATSIPTB0
0x88 W 0x00 TSI Data Reference Low Byte B
ATSIPTB1
0x89 W 0x00 TSI Data Reference High Byte B
AEOMC
0x8A W 0x00 EOM Control
AEOMDTLEN 0x8B W 0x00 EOM Data Length Limit
Digital Receiver B
Global register
BDIGRXC
0x8C W 0x00 Global Settings
Page
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149
Data Sheet
132
Version 4.0, 2007-06-01