TDA5230 Datasheet, PDF (175/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Specifications
Table 7
Characteristics of Digital Data Filter and Data Clock Recovery
The following Specification values are evaluated with ASK 2kBit, ASK 9.6 kBit, FSK 9.6 kBit & D ±35 kHz.
Acceptance Criteria is: MER < 10 %
#
Parameter
Symbol
H.1 Data-Rate of received Telegram b
(nominal)
H.2 Data-Rate Error of received
Telegram
(Adjusted Data-Rate vs. Data-Rate of
received Telegram)
Sensitivity Loss < 1 dB
Db
H.3 Duty-Cycle Error of manchester
coding of received Telegram
(Value describes duration of first chip
in respect to bit duration)
Limit Values
Unit
min. typ. max.
0.5
20
kbit/s
Test Case
*
*
*
-10
10
%
DRE -10% & DC 50%
DRE 0% & DC 50%
DRE +10% & DC 50%
*
Sensitivity Loss < 1 dB
tolManchester1 45
Sensitivity Loss < 3 dB
tolManchester2 35
55
%
DRE -10% & DC 45%
DRE -10% & DC 55%
DRE 0% & DC 45%
DRE 0% & DC 55%
DRE +10% & DC 45%
DRE +10% & DC 55%
65
%
DRE -10% & DC 35%
DRE -10% & DC 65%
DRE 0% & DC 35%
DRE 0% & DC 65%
DRE +10% & DC 35%
DRE +10% & DC 65%
Table 8
Characteristics of Digital FSK-Demodulator
The following Specification values are evaluated with FSK 9.6kBit & D ±35 kHz .
#
Parameter
Symbol
I.1 FSK demodulator center
frequency
(nominal)
I.2 FSK demodulator input range
f_FSKcenter
D_fFSKspan
(Offset from nominal IF center
frequency, where Signal-Power at
output of Matched Data Filter (average
of 500 readouts of value in register
ASKNP) does not decrease by more
than 3dB from Signal-Power at IF
center frequency)
Limit Values
Unit
min. typ. max.
10.7
MHz
Test Case
*
*
-100
100
kHz
DRE 0% & DC 50% *
10 mVeff at Pins LIM-
IN- vs. LIM-IN+
Data Sheet
171
Version 4.0, 2007-06-01