TDA5230 Datasheet, PDF (110/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
valid data
RUNIN
TSI A
< 1bit
clock recovery reset
start point
all space or all mark
valid data
TSI GAP
PLL sync
GAPSync
TSI B
< 1bit
Figure 54
internal PLL sync
Clock Recovery GAP Re-synchronization Mode 1
When the time TSI GAP in the start sequence of the transmitted telegram has elapsed,
the receiver needs a certain time (GAPSync = 5...6 chips) to readjust the PLL settings.
Behavior of the system at the starting position of the TSI B:
The starting position (TSI B start) for the TSI B comparison is independent from the
RUNIN settings (CDR2 register) and the Re-synchronization mode (TSIMODE register):
TSIBstart[chips] = TSIGAP[chips] + 6…8
The incoming chips at TSI B start and the following incoming chips are compared with
the contents of the register TSI B. Please notice that the receiver’s PLL runs at the data
rate determined before the gap. Therefore, the receiver calculates the gap based on this
data rate.
Behavior of the system at the ending position of TSI B:
The system checks for the TSI B to match within a limited time. If there is no match within
this time, then the receiver starts again to search for the TSI A pattern at the following
incoming chips:
TSIBstop[chips] = TSIGAP[chips] + TSILENB[chips] + 11
For a successful TSI B pattern match, the defined TSI B pattern must be between “Start
of TSIB” and “Stop of TSI B”. In the example below, the earliest possible start position
would be the 18^th chip and the latest possible start position would be the 22^nd chip.
Please note that after a gap the internal TSI comparison register is cleared (all chips set
to ’0’). In this case, a TSI B criteria of “0000” would always match at the beginning. To
avoid such an unwanted matching, set the highest TSI B match chip to ’1’.
Data Sheet
106
Version 4.0, 2007-06-01