TDA5230 Datasheet, PDF (156/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Register Descriptions
Dual: APSLC and BPSLC: Pre Slicer Control
ADDR: 0xB4 and 0xB5
Reset Value: 0x00
Bit R/W Description
7 W PSLCDA: Pre-Slicer disable
0: Pre-Slicer enable: only used in combination with TSI GAP Mode using
standard settings as below!
1: Pre-Slicer disable (default)
6:5 W PSLCHYS: Pre-Slicer hysteresis
use 01b
4:0 W PSLCTHR: Pre-Slicer disable threshold
use 10010 (0x12).
Dual: ASIGDETLO and BSIGDETLO: Signal Detector Threshold Low Level
ADDR: 0xB6 and 0xB7
Reset Value: 0x00
Bit R/W Description (For detailed procedure refer to application note.)
7 W SDLORE: Source selection of ASK Noise Power status register
0: ASK Noise for SIGDET0/1
1: Signal for minimal usable FSK deviation
If enabled, the SIGDET low level can be read out from ASKNP register
6 W SDSEL: Manual selection of SIGDET range¹⁾
0: Disable(default) - SIGDET0/1 range selection factor automatically done;
depending on data rate
1: Enable - Use SIGDETSEL control to set the valid range
5:0 W SDLOTHR: Signal Detector Threshold Low Level.
This threshold level is only valid if the FSK Noise detector selection in the
NDCONFIG register is set to “11b”
See application notes “How to choose an Application specific Signal Detection
Threshold for TDA523x based ASK Mode Applications” and “How to Choose an
Application Specific Signal- and Noise-Detection Threshold for TDA523x based FSK
Mode Applications” for specific procedure to determine this threshold by application.
1) Use default value
Data Sheet
152
Version 4.0, 2007-06-01