TDA5230 Datasheet, PDF (121/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

TDA523x
Functional Description
Known Problem on using FIFO Lock in combination with EOM Interrupt in Run
Mode Slave:
Indifferent to the described behavior in Run Mode Slave, the NINT sticks low for low
active Interrupt or high for high active interrupt, after an EOM Interrupt, if FIFO Lock is
enabled. NINT is reset after reading the FIFO. See also Chapter 2.4.17 Interrupt
Generation Unit.
FIFO Status Word
The FIFO Status Word is mixed to FIFO SPI transmission, and shows if there was an
overflow, and how many valid data bits are transmitted. The number of valid FIFO bits is
indicated at bit positions S0 to S5. S6 of the Status Word is always undefined.
SDI
I7 I6
SDO
high impedance Z
I1 I0
32 FIFO Bits
Status Word
D0 D1
D30 D31 S7 S6
S1 S0
Figure 62 SPI Data FIFO Read
If the Write Address Pointer outruns the Read Address Pointer, an overflow is indicated
in the FIFO Overflow Status bit in the FIFO Read Status Word at position S7. All 32 FIFO
bits and the bits S5 to S0 of the Status Word are undefined while the Overflow Status bit
is set.
If a TSI is detected after an overflow, the FIFO Overflow Status bit is cleared and the
entire data FIFO is initialized.
Initialization
Additionally there are two possibilities to initialize the Data FIFO.
• If the INITFIFO bit is set in the CMC0 register(“Init FIFO at Cycle Start”) the entire
Data FIFO is always initialized
a.) after switching to Run Mode Slave or
b.) switching from Self Polling Mode to Run Mode Self Polling.
• If the FSINITFIFO-bit in CMC1 register is set, the entire Data FIFO is initialized when
a TSI is detected and the Data FIFO is not locked (“Init FIFO at Frame Start”).
Data Sheet
117
Version 4.0, 2007-06-01