TDA5230 Datasheet, PDF (129/186 Pages) Infineon Technologies AG – Universal Low Power ASK/FSK Single Conversion Multi-Channel Image-Reject Receiver

SPIAT: SPI Address Tracer
ADDR: 0x00
Bit R/W Description
7:0 R Address Tracer Register
SPIDT: SPI Data Tracer
ADDR: 0x01
Bit R/W Description
7:0 R Data Tracer Register
TDA523x
Functional Description
Reset Value: 0x00
Reset Value: 0x00
Read FIFO
NCS
Frame
1
81
32 1
8
SCK
Instruction
SDI
I7 I6
SDO
high impedance Z
I1 I0
32 FIFO Bits
Status Word
D0 D1
D30 D31 S7 S6
S1 S0
Frame
1
81
32 1
8
Instruction
I7 I6
I1 I0
32 FIFO Bits
Status Word
D0 D1
D30 D31 S7 S6
S1 S0
Figure 68 Read FIFO
To read the FIFO, the chip must be selected first. Therefore, the master must set the
NCS line to low. After this, the instruction byte is shifted in on SDI and stored in the
internal instruction register. The data bits of the FIFO are then shifted out on SDO. The
following byte is a status word that contains the number of valid bits in the data packet.
After completing the read operation, the master sets the NCS line to high.
Instruction Set
Instruction
WR
RD
RDF
Description
Write to chip
Read from chip
Read FIFO from chip
Instruction Format
0000 0010
0000 0011
0000 0100
Data Sheet
125
Version 4.0, 2007-06-01