Z8F0830HH020SG Datasheet, PDF (99/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
81
tion and reload events. The user can configure the timer interrupt to be generated only
at the input deassertion event or the reload event by setting the TICONFIG field of the
TxCTL1 Register.
5. Configure the associated GPIO port pin for the timer input alternate function.
6. Write to the Timer Control Register to enable the timer.
7. Assert the timer input signal to initiate the counting.
CAPTURE/COMPARE Mode
In CAPTURE/COMPARE Mode, the timer begins counting on the first external timer
input transition. The acceptable transition (rising edge or falling edge) is set by the TPOL
bit in the Timer Control Register. The timer input is the system clock.
Every subsequent acceptable transition (after the first) of the timer input signal, captures
the current count value. The capture value is written to the timer PWM High and Low
Byte registers. When the capture event occurs, an interrupt is generated, the count value in
the Timer High and Low Byte registers is reset to 0001H and the counting resumes. The
INPCAP bit in the TxCTL1 Register is set to indicate that the timer interrupt is caused by
an input capture event.
If no capture event occurs, the timer counts up to the 16-bit compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the compare value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001H and counting resumes. The INPCAP bit in the TxCTL1 Register is cleared to indi-
cate that the timer interrupt has not been caused by an input capture event.
Observe the following steps for configuring a timer for CAPTURE/COMPARE Mode and
for initiating the count:
1. Write to the Timer Control Register to:
– Disable the timer
– Configure the timer for CAPTURE/COMPARE Mode.
– Set the prescale value.
– Set the capture edge (rising or falling) for the timer input.
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
cally 0001H).
3. Write to the Timer Reload High and Low Byte registers to set the compare value.
4. Enable the timer interrupt and set the timer interrupt priority by writing to the relevant
interrupt registers.By default, the timer interrupt are generated for both input capture
and Reload events. The user can configure the timer interrupt to be generated only at
the input capture event or the reload event by setting TICONFIG field of the TxCTL1
Register.
5. Configure the associated GPIO port pin for the timer input alternate function.
PS025113-1212
Operation