Z8F0830HH020SG Datasheet, PDF (40/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
22
Table 9. Reset and Stop Mode Recovery Characteristics and Latency
Reset Characteristics and Latency
Reset Type
Control Registers eZ8 CPU Reset Latency (Delay)
System Reset
Reset (as applicable) Reset
About 66 Internal Precision Oscillator
Cycles
System Reset with Crystal Reset (as applicable) Reset
Oscillator Enabled
About 5000 Internal Precision Oscillator
Cycles
Stop Mode Recovery
Unaffected, except
WDT_CTL and
OSC_CTL registers
Reset
About 66 Internal Precision Oscillator
cycles
Stop Mode Recovery with Unaffected, except
crystal oscillator enabled WDT_CTL and
OSC_CTL registers
Reset
About 5000 Internal Precision Oscillator
cycles
During a system RESET or Stop Mode Recovery, the Z8 Encore! F0830 Series device is
held in reset for about 66 cycles of the Internal Precision Oscillator. If the crystal oscillator
is enabled in the Flash option bits, the reset period is increased to about 5000 IPO cycles.
When a reset occurs because of a low voltage condition or Power-On Reset, the reset delay
is measured from the time that the supply voltage first exceeds the POR level (discussed
later in this chapter). If the external pin reset remains asserted at the end of the reset
period, the device remains in reset until the pin is deasserted.
At the beginning of reset, all GPIO pins are configured as inputs with pull-up resistor dis-
abled, except PD0 which is shared with the reset pin. On reset, the Port D0 pin is config-
ured as a bidirectional open-drain reset. This pin is internally driven low during port reset,
after which the user code may reconfigure this pin as a general purpose output.
During reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watchdog Timer Oscillator continues to run.
On reset, control registers within the register file that have a defined reset value are loaded
with their reset values. Other control registers (including the Stack Pointer, Register
Pointer and Flags) and general purpose RAM are undefined following the reset. The eZ8
CPU fetches the reset vector at program memory addresses 0002H and 0003H and loads
that value into the program counter. Program execution begins at the reset vector address.
Because the control registers are reinitialized by a system reset, the system clock after
reset is always the IPO. User software must reconfigure the oscillator control block, to
enable and select the correct system clock source.
PS025113-1212
Reset Types