Z8F0830HH020SG Datasheet, PDF (80/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
62
IRQ1 Enable High and Low Bit Registers
Table 41 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit reg-
isters, shown in Tables 42 and 43, form a priority-encoded enabling service for interrupts
in the Interrupt Request 1 Register. Priority is generated by setting the bits in each register.
Table 41. IRQ1 Enable and Priority Encoding
IRQ1ENH[x] IRQ1ENL[x]
Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
Note: x indicates register bits in the address range 7–0.
Table 42. IRQ1 Enable High Bit Register (IRQ1ENH)
Bit
Field
RESET
R/W
Address
7
6
5
PA7ENH PA6CENH PA5ENH
0
0
0
R/W
R/W
R/W
4
3
PA4ENH PA3ENH
0
0
R/W
R/W
FC4H
2
PA2ENH
0
R/W
1
PA1ENH
0
R/W
0
PA0ENH
0
R/W
Bit
Description
[7]
PA7ENH
Port A Bit[7] Interrupt Request Enable High Bit
[6]
Port A Bit[7] or Comparator Interrupt Request Enable High Bit
PA6CENH
[5:0]
PAxENH
Port A Bit[x] Interrupt Request Enable High Bit
See the interrupt port select register for selection of either Port A or Port D as the interrupt
source.
Note: x indicates register bits in the address range 5–0.
PS025113-1212
Interrupt Control Register Definitions