Z8F0830HH020SG Datasheet, PDF (81/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
63
Table 43. IRQ1 Enable Low Bit Register (IRQ1ENL)
Bit
Field
RESET
R/W
Address
7
PA7ENL
0
R/W
6
PA6CENL
0
R/W
5
PA5ENL
0
R/W
4
3
PA4ENL PA3ENL
0
0
R/W
R/W
FC5H
2
PA2ENL
0
R/W
1
PA1ENL
0
R/W
0
PA0ENL
0
R/W
Bit
Description
[7]
PA7ENL
Port A Bit[7] Interrupt Request Enable Low Bit
[6]
Port A Bit[7] or Comparator Interrupt Request Enable Low Bit
PA6CENL
[5:0]
PAxENL
Port A Bit[x] Interrupt Request Enable Low Bit
See the interrupt port select register for selection of either Port A or Port D as the interrupt
source.
Note: x indicates register bits in the address range 5–0.
IRQ2 Enable High and Low Bit Registers
Table 44 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit reg-
isters, shown in Tables 45 and 46, form a priority-encoded enabling service for interrupts
in the Interrupt Request 2 Register. Priority is generated by setting the bits in each register.
Table 44. IRQ2 Enable and Priority Encoding
IRQ2ENH[x] IRQ2ENL[x]
Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
Note: x indicates register bits in the address range 7–0.
PS025113-1212
Interrupt Control Register Definitions