Z8F0830HH020SG Datasheet, PDF (93/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
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PWM Period (s) = -------R----e---l--o---a--d-----V----a---l--u---e----^-----P---r--e---s--c---a--l--e--------
System Clock Frequency (Hz)
If an initial starting value other than 0001H is loaded into the Timer High and Low Byte
registers, use the ONE-SHOT Mode equation to determine the first PWM time-out period.
If TPOL bit is set to 0, the ratio of the PWM output high time to the total period is repre-
sented by:
PWM Output High Time Ratio (%) = ^{R-----e--l--o---a---d----V----a---l--u---e----–----P----W-----M-------V-----a--l--u---e-}  100
Reload Value
If TPOL bit is set to 1, the ratio of the PWM output high time to the total period is repre-
sented by:
PWM Output High Time Ratio (%) = --P---W------M-------V----a---l-u---e---  100
Reload Value
PWM DUAL OUTPUT Mode
In PWM DUAL OUTPUT Mode, the timer outputs a PWM output signal pair (basic
PWM signal and its complement) through two GPIO port pins. The timer input is the sys-
tem clock. The timer first counts up to 16-bit PWM match value stored in the timer PWM
High and Low Byte registers. When the timer count value matches the PWM value, the
timer output toggles. The timer continues counting until it reaches the reload value stored
in the Timer Reload High and Low Byte registers. Upon reaching the reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to 0001H and counting resumes.
If the TPOL bit in the Timer Control Register is set to 1, the timer output signal begins as
a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The
timer output signal returns to a High (1) after the timer reaches the reload value and is
reset to 0001H.
If the TPOL bit in the Timer Control Register is set to 0, the timer output signal begins as
a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The
timer output signal returns to a Low (0) after the timer reaches the reload value and is reset
to 0001H.
The timer also generates a second PWM output signal: the timer output complement. The
timer output complement is the complement of the timer output PWM signal. A program-
mable deadband delay can be configured to time delay (0 to 128 system clock cycles)
PWM output transitions on these two pins from a Low to a High (inactive to active) to
ensure a time gap between the deassertion of one PWM output to the assertion of its com-
plement.
PS025113-1212
Operation