Z8F0830HH020SG Datasheet, PDF (155/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
137
Power Failure Protection
NVDS routines employ error-checking mechanisms to ensure that any power failure will
only endanger the most recently written byte. Bytes previously written to the array are not
perturbed. For this protection to function, the VBO must be enabled (see the Low-Power
Modes chapter on page 30) and configured for a threshold voltage of 2.4 V or greater (see
the Trim Bit Address Space section on page 129).
A system reset (such as a pin reset or Watchdog Timer reset) that occurs during a write
operation also perturbs the byte currently being written. All other bytes in the array are
unperturbed.
Optimizing NVDS Memory Usage for Execution Speed
As indicated in Table 93, the NVDS read time varies drastically; this discrepancy being a
trade-off for minimizing the frequency of writes that require post-write page erases. The
NVDS read time of address N is a function of the number of writes to addresses other than
N since the most recent write to address N as well as the number of writes since the most
recent page erase. Neglecting the effects caused by page erases and results caused by the
initial condition in which the NVDS is blank, a rule of thumb to consider is that every
write since the most recent page erase causes read times of unwritten addresses to increase
by 0.8 µs up to a maximum of 258 µs.
Table 93. NVDS Read Time
Operation
Read
Write
Illegal Read
Illegal Write
Minimum
Latency (µs)
71
126
6
7
Maximum
Latency (µs)
258
136
6
7
Note: For every 200 writes, a maintenance operation is necessary. In this rare occurrence, the
write takes up to 58 ms to complete.
If NVDS read performance is critical to your software architecture, you can optimize your
code for speed by using either of the two methods listed below.
1. Periodically refresh all addresses that are used; this is the more useful method. The
optimal use of NVDS, in terms of speed, is to rotate the writes evenly among all
addresses planned for use, thereby bringing all reads closer to the minimum read time.
PS025113-1212
NVDS Code Interface