Z8F0830HH020SG Datasheet, PDF (101/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
83
Timer Control Register Definitions
This section defines the features of the following Timer Control registers.
Timer 0–1 High and Low Byte Registers: see page 83
Timer Reload High and Low Byte Registers: see page 85
Timer 0–1 PWM High and Low Byte Registers: see page 86
Timer 0–1 Control Registers: see page 87
Timer 0–1 High and Low Byte Registers
The Timer 0–1 High and Low Byte (TxH and TxL) registers, shown in Tables 50 and 51,
contain the current 16-bit timer count value. When the timer is enabled, a read from TxH
causes the value in TxL to be stored in a temporary holding register. A read from TxL
always returns this temporary register content when the timer is enabled; however, when
the timer is disabled, a read from the TxL reads the TxL Register content directly.
Writing to the Timer High and Low Byte registers while the timer is enabled is not recom-
mended. There are no temporary holding registers available for write operations; there-
fore, simultaneous 16-bit writes are not possible. If either the timer High or Low Byte
registers are written during counting, the 8-bit written value is placed in the counter (High
or Low byte) at the next clock edge. The counter continues counting from the new value.
Table 50. Timer 0–1 High Byte Register (TxH)
Bit
7
6
5
4
3
2
1
0
Field
TH
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F00H, F08H
Table 51. Timer 0–1 Low Byte Register (TxL)
Bit
7
6
5
4
3
2
1
0
Field
TL
RESET
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F01H, F09H
PS025113-1212
Timer Control Register Definitions