Z8F0830HH020SG Datasheet, PDF (189/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
171
eZ8 CPU Instruction Summary
Table 113 summarizes the eZ8 CPU instructions. The table identifies the addressing
modes employed by the instruction, the effect upon the Flags register, the number of CPU
clock cycles required for the instruction fetch and the number of CPU clock cycles
required for the instruction execution.
Table 113. eZ8 CPU Instruction Summary
Assembly
Mnemonic
ADC dst, src
Symbolic Operation
dst ← dst + src + C
Address
Mode
dst src
r
r
r Ir
RR
R IR
R IM
ADCX dst, src dst ← dst + src + C
IR IM
ER ER
ADD dst, src dst ← dst + src
ER IM
r
r
r Ir
RR
R IR
R IM
ADDX dst, src dst ← dst + src
IR IM
ER ER
ER IM
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
Op
Code(s)
(Hex)
12
13
14
15
16
17
18
19
02
03
04
05
06
07
08
09
Flags
Fetch Instr.
C Z S V D H Cycles Cycles
****0* 2
3
2
4
3
3
3
4
3
3
3
4
****0* 4
3
4
3
****0* 2
3
2
4
3
3
3
4
3
3
3
4
****0* 4
3
4
3
PS025113-1212
eZ8 CPU Instruction Summary