Z8F0830HH020SG Datasheet, PDF (49/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
31
HALT Mode
Executing the eZ8 CPU HALT instruction places the device into HALT Mode. In HALT
Mode, the operating characteristics are:
• Primary oscillator is enabled and continues to operate
• System clock is enabled and continues to operate
• eZ8 CPU is stopped
• Program counter (PC) stops incrementing
• Watchdog Timer’s internal RC oscillator continues to operate
• If enabled, the Watchdog Timer continues to operate
• All other on-chip peripherals continue to operate
The eZ8 CPU can be brought out of HALT Mode by any one of the following operations:
• Interrupt
• Watchdog Timer time-out (interrupt or reset)
• Power-On Reset
• Voltage Brown-Out reset
• External RESET pin assertion
To minimize current in HALT Mode, all GPIO pins that are configured as digital inputs
must be driven to V_DD when pull-up register bit is enabled or to one of power rail (V_DD or
GND) when pull-up register bit is disabled.
Peripheral Level Power Control
In addition to the STOP and HALT modes, it is possible to disable each peripheral on each
of the Z8 Encore! F0830 Series devices. Disabling a given peripheral minimizes its power
consumption.
Power Control Register Definitions
Power Control Register 0
Each bit of the following registers disables a peripheral block, either by gating its system
clock input or by removing power from the block.
PS025113-1212
HALT Mode