Z8F0830HH020SG Datasheet, PDF (106/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
88
Bit
[0]
INPCAP
Description (Continued)
Input Capture Event
This bit indicates whether the most recent timer interrupt is caused by a timer input capture
event.
0 = Previous timer interrupt is not caused by timer input capture event.
1 = Previous timer interrupt is caused by timer input capture event.
Timer 0–1 Control Register 1
The Timer 0–1 Control (TxCTL1) registers enable/disable the timers, set the prescaler
value, and determine the timer operating mode.
Table 57. Timer 0–1 Control Register 1 (TxCTL1)
Bit
7
6
5
4
3
Field
TEN
TPOL
PRES
RESET
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Address
F07H, F0FH
2
1
0
TMODE
0
0
0
R/W
R/W
R/W
Bit
[7]
TEN
Description
Timer Enable
0 = Timer is disabled.
1 = Timer enabled to count.
PS025113-1212
Timer Control Register Definitions