Z8F0830HH020SG Datasheet, PDF (61/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
43
Bit
Field
RESET
R/W
Address
Port A–D Output Control Subregisters
The Port A–D Output Control Subregister, shown in Table 23, is accessed through the Port
A–D Control Register by writing 03H to the Port A–D Address Register. Setting the bits in
the Port A–D Output Control subregisters to 1 configures the specified port pins for open-
drain operation. These subregisters affect the pins directly and, as a result, alternate func-
tions are also affected.
Table 23. Port A–D Output Control Subregisters (PxOC)
7
6
5
4
3
2
1
0
POC7 POC6 POC5 POC4 POC3 POC2 POC1 POC0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 03H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit
Description
[7:0]
POCx
Port Output Control
These bits function independently of the Alternate function bit and always disable the drains, if
set to 1.
0 = The drains are enabled for any OUTPUT Mode (unless overridden by the Alternate func-
tion).
1 = The drain of the associated pin is disabled (OPEN-DRAIN mode).
Note: x indicates the specific GPIO port pin number (7–0).
PS025113-1212
GPIO Control Register Definitions