Z8F0830HH020SG Datasheet, PDF (71/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
53
Interrupt Controller
The Interrupt Controller on the Z8 Encore!^® F0830 Series products prioritize the interrupt
requests from the on-chip peripherals and the GPIO port pins. The features of the Interrupt
Controller include:
• Seventeen interrupt sources using sixteen unique interrupt vectors:
– Twelve GPIO port pin interrupt sources
– Five on-chip peripheral interrupt sources (Comparator Output interrupt shares one
interrupt vector with PA6)
• Flexible GPIO interrupts
– Eight selectable rising and falling edge GPIO interrupts
– Four dual-edge interrupts
• Three levels of individually programmable interrupt priority
• Watchdog Timer can be configured to generate an interrupt
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Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt
service routine is involved with the exchange of data, status information or control infor-
mation between the CPU and the interrupting peripheral. When the service routine is com-
pleted, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the Interrupt Controller has no effect on operation. For more information about interrupt
servicing by the eZ8 CPU, refer to the eZ8 CPU User Manual (UM0128), which is avail-
able for download at www.zilog.com.
Interrupt Vector Listing
Table 34 lists the interrupts available in order of priority. The interrupt vector is stored
with the most significant byte (MSB) at the even program memory address and the least
significant byte (LSB) at the odd program memory address.
Note: Some port interrupts are not available on the 20-pin and 28-pin packages. The ADC inter-
rupt is unavailable on devices not containing an ADC.
PS025113-1212
Interrupt Controller