Z8F0830HH020SG Datasheet, PDF (159/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
141
RS-232 TX
RS-232 RX
RS-232
Transceiver
VDD
Open-Drain
Buffer
10KΩ
DBG Pin
Figure 22. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, #2 of 2
DEBUG Mode
The operating characteristics of the devices in DEBUG Mode are:
• The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to ex-
ecute specific instructions
• The system clock operates, unless the device is in STOP Mode
• All enabled on-chip peripherals operate, unless the device is in STOP Mode
• Automatically exits HALT Mode
• Constantly refreshes the Watchdog Timer, if enabled
Entering DEBUG Mode
• The device enters DEBUG Mode after the eZ8 CPU executes a Breakpoint (BRK) in-
struction
• If the DBG pin is held low during the most recent clock cycle of system reset, the de-
vice enters DEBUG Mode on exiting system reset
Exiting DEBUG Mode
The device exits DEBUG Mode following any of these operations:
• Clearing the DBGMODE bit in the OCD Control Register to 0
• Power-On Reset
• Voltage Brown-Out reset
PS025113-1212
Operation