Z8F0830HH020SG Datasheet, PDF (105/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
87
Timer 0–1 Control Registers
The Timer Control registers are 8-bit read/write registers that control the operation of their
associated counter/timers.
Time 0–1 Control Register 0
The Timer Control 0 (TxCTL0) and Timer Control 1 (TxCTL1) registers determine the
timer operating mode. These registers also include a programmable PWM deadband delay,
two bits to configure the timer interrupt definition, and a status bit to identify if the most
recent timer interrupt is caused by an input capture event.
Table 56. Timer 0–1 Control Register 0 (TxCTL0)
Bit
7
Field
TMODEHI
RESET
0
R/W
R/W
Address
6
5
TICONFIG
0
0
R/W
R/W
4
3
Reserved
0
0
R/W
R/W
F06H, F0EH
2
PWMD
0
R/W
1
0
INPCAP
0
0
R/W
R/W
Bit
[7]
TMODEHI
[6:5]
TICONFIG
[4]
[3:1]
PWMD
Description
Timer Mode High Bit
This bit along with the TMODE field in the TxCTL1 Register determines the operating mode
of the timer. This is the most significant bit of the timer mode selection value. See the
TxCTL1 Register description on the next page for additional details.
Timer Interrupt Configuration
This field configures timer interrupt definition.
0x = Timer interrupt occurs on all of the defined reload, compare and input events.
10 = Timer interrupt occurs only on defined input capture/deassertion events.
11 = Timer interrupt occurs only on defined reload/compare events.
Reserved
This bit is reserved and must be programmed to 0.
PWM Delay Value
This field is a programmable delay to control the number of system clock cycles delay
before the timer output and the timer output complement are forced to their Active state.
000 = No delay.
001 = 2 cycles delay.
010 = 4 cycles delay.
011 = 8 cycles delay.
100 = 16 cycles delay.
101 = 32 cycles delay.
110 = 64 cycles delay.
111 = 128 cycles delay.
PS025113-1212
Timer Control Register Definitions