Z8F0830HH020SG Datasheet, PDF (64/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
46
Port A–D Pull-up Enable Subregisters
The Port A–D Pull-Up Enable Subregister is accessed through the Port A–D Control Reg-
ister by writing 06H to the Port A–D Address Register. See Table 26. Setting the bits in the
Port A–D Pull-Up Enable subregisters enables a weak internal resistive pull-up on the
specified port pins.
Table 26. Port A–D Pull-Up Enable Subregisters (PxPUE)
Bit
Field
RESET
R/W
Address
7
6
5
4
3
2
1
0
PPUE7 PPUE6 PPUE5 PPUE4 PPUE3 PPUE2 PPUE1 PPUE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 06H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit
Description
[7:0]
PxPUE
Port Pull-Up Enable
0 = The weak pull-up on the port pin is disabled.
1 = The weak pull-up on the port pin is enabled.
Note: x indicates the specific GPIO port pin number (7–0).
PS025113-1212
GPIO Control Register Definitions