Z8F0830HH020SG Datasheet, PDF (96/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
78
5. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input capture and Reload events. If appropriate, configure the timer interrupt to be
generated only at the input capture event or the reload event by setting the TICONFIG
field of the TxCTL1 Register.
6. Configure the associated GPIO port pin for the timer input alternate function.
7. Write to the Timer Control Register to enable the timer and initiate counting.
In CAPTURE Mode, the elapsed time between the timer start and the capture event can be
calculated using the following equation:
Capture Elapsed Time (s) = ^---C----a---p---t-u---r--e----V-----a--l--u---e----–-----S---t--a---r--t---V----a---l-u---e----^---^-----P---r--e---s--c---a---l-e-
System Clock Frequency (Hz)
CAPTURE RESTART Mode
In CAPTURE RESTART Mode, the current timer count value is recorded when the
acceptable external timer input transition occurs. The capture count value is written to the
timer PWM High and Low Byte registers. The timer input is the system clock. The TPOL
bit in the Timer Control Register determines whether the capture occurs on a rising edge
or a falling edge of the timer input signal. When the capture event occurs, an interrupt is
generated and the count value in the Timer High and Low Byte registers is reset to 0001H
and counting resumes. The INPCAP bit in the TxCTL1 Register is set to indicate that the
timer interrupt has been caused by an input capture event.
If no capture event occurs, the timer counts up to 16-bit compare value stored in the Timer
Reload High and Low Byte registers. Upon reaching the reload value, the timer generates
an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H
and counting resumes. The INPCAP bit in the TxCTL1 Register is cleared to indicate that
the timer interrupt has not been caused by an input capture event.
Observe the following steps for configuring a timer for CAPTURE RESTART Mode and
for initiating the count:
1. Write to the Timer Control Register to:
– Disable the timer
– Configure the timer for CAPTURE RESTART Mode; setting the mode also
involves writing to TMODEHI bit in the TxCTL1 Register
– Set the prescale value
– Set the capture edge (rising or falling) for the timer input
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
cally 0001H).
PS025113-1212
Operation