Z8F0830HH020SG Datasheet, PDF (76/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
58
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) Register, shown in Table 35 stores the interrupt requests
for both vectored and polled interrupts. When a request is sent to the Interrupt Controller,
the corresponding bit in the IRQ0 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the Interrupt Controller passes an interrupt request to the eZ8 CPU.
If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 0 Register to determine if any interrupt requests are pending.
Table 35. Interrupt Request 0 Register (IRQ0)
Bit
7
6
5
4
3
2
1
0
Field
Reserved T1I
T0I
Reserved
ADCI
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FC0H
Bit
[7]
[6]
T1I
[5]
T0I
[4:1]
[0]
ADCI
Description
Reserved
This bit is reserved and must be programmed to 0.
Timer 1 Interrupt Request
0 = No interrupt request is pending for timer 1.
1 = An interrupt request from timer 1 is awaiting service.
Timer 0 Interrupt Request
0 = No interrupt request is pending for timer 0.
1 = An interrupt request from timer 0 is awaiting service.
Reserved
These registers are reserved and must be programmed to 0000.
ADC Interrupt Request
0 = No interrupt request is pending for the analog-to-digital converter.
1 = An interrupt request from the analog-to-digital converter is awaiting service.
PS025113-1212
Interrupt Control Register Definitions