Z8F0830HH020SG Datasheet, PDF (44/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
26
clock and reset signals, the required reset duration may be three or four clock periods. A
reset pulse of three clock cycles in duration might trigger a reset and a reset pulse of four
cycles in duration always triggers a reset.
While the RESET input pin is asserted low, the Z8 Encore! F0830 Series devices remain
in the Reset state. If the RESET pin is held low beyond the system reset time-out, the
device exits the Reset state on the system clock rising edge following RESET pin deasser-
tion. Following a system reset initiated by the external RESET pin, the EXT status bit in
the Reset Status (RSTSTAT) Register is set to 1.
External Reset Indicator
During system reset or when enabled by the GPIO logic, the RESET pin functions as an
open-drain (active low) RESET mode indicator in addition to the input functionality. This
reset output feature allows an Z8 Encore! F0830 Series device to reset other components
to which it is connected, even if that reset is caused by internal sources such as POR, VBO
or WDT events. See the Port A–D Control Registers section on page 41.
After an internal Reset event occurs, the internal circuitry begins driving the RESET pin
low. The RESET pin is held low by the internal circuitry until the appropriate delay listed
in Table 9 (see page 22) has elapsed.
On-Chip Debugger Initiated Reset
A Power-On Reset can be initiated using the On-Chip Debugger by setting the RST bit in
the OCD Control Register. The OCD block is not reset, but the remainder of the chip goes
through a normal system reset. The RST bit automatically clears during the system reset.
Following the system reset, the POR bit in the Reset Status (RSTSTAT) Register is set.
Stop Mode Recovery
The device enters the STOP Mode when the STOP instruction is executed by the eZ8
CPU. See the Low-Power Modes chapter on page 30 for detailed STOP Mode informa-
tion. During Stop Mode Recovery, the CPU is held in reset for about 66 IPO cycles if the
crystal oscillator is disabled or about 5000 cycles if it is enabled.
Stop Mode Recovery does not affect the on-chip registers other than the Reset Status
(RSTSTAT) Register and the Oscillator Control Register (OSCCTL). After any Stop
Mode Recovery, the IPO is enabled and selected as the system clock. If another system
clock source is required or IPO disabling is required, the Stop Mode Recovery code must
reconfigure the oscillator control block such that the correct system clock source is
enabled and selected.
PS025113-1212
Stop Mode Recovery