Z8F0830HH020SG Datasheet, PDF (77/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
59
Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) Register, shown in Table 36, stores interrupt requests for
both vectored and polled interrupts. When a request is sent to the Interrupt Controller, the
corresponding bit in the IRQ1 Register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the Interrupt Controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 1 Register to determine if any interrupt requests are pending.
Table 36. Interrupt Request 1 Register (IRQ1)
Bit
Field
RESET
R/W
Address
7
PA7I
0
R/W
6
PA6CI
0
R/W
5
PA5I
0
R/W
4
3
PA4I
PA3I
0
0
R/W
R/W
FC3H
2
PA2I
0
R/W
1
PA1I
0
R/W
0
PA0I
0
R/W
Bit
Description
[7]
PA7I
Port A7
0 = No interrupt request is pending for GPIO Port A.
1 = An interrupt request from GPIO Port A.
[6]
PA6CI
Port A6 or Comparator Interrupt Request
0 = No interrupt request is pending for GPIO Port A or comparator.
1 = An interrupt request from GPIO Port A or comparator.
[5]
PAxI
Port A Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port A pin x.
1 = An interrupt request from GPIO Port A pin x is awaiting service.
Note: x indicates the specific GPIO port pin number (5–0).
PS025113-1212
Interrupt Control Register Definitions