Z8F0830HH020SG Datasheet, PDF (37/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
19
Table 8. Register File Address Map (Continued)
Address (Hex) Register Description
Interrupt Controller (cont’d)
FCE
Shared interrupt select
FCF
Interrupt control
GPIO Port A
FD0
FD1
FD2
Port A address
Port A control
Port A input data
FD3
Port A output data
GPIO Port B
FD4
Port B address
FD5
Port B control
FD6
Port B input data
FD7
Port B output data
GPIO Port C
FD8
FD9
FDA
FDB
Port C address
Port C control
Port C input data
Port C output data
GPIO Port D
FDC
FDD
Port D address
Port D control
FDE
FDF
Reserved
Port D output data
FE0–FEF
Reserved
Watchdog Timer (WDT)
FF0
Reset status
Watchdog Timer control
FF1
Watchdog Timer reload upper byte
FF2
Watchdog Timer reload high byte
FF3
Watchdog Timer reload low byte
FF4–FF5
Reserved
Note: XX = Undefined.
Mnemonic Reset (Hex)
IRQSS
00
IRQCTL
00
PAADDR
00
PACTL
00
PAIN
XX
PAOUT
00
PBADDR
00
PBCTL
00
PBIN
XX
PBOUT
00
PCADDR
00
PCCTL
00
PCIN
XX
PCOUT
00
PDADDR
00
PDCTL
00
—
XX
PDOUT
00
—
XX
RSTSTAT
XX
WDTCTL
XX
WDTU
FF
WDTH
FF
WDTL
FF
—
XX
Page No.
66
67
39
41
41
41
39
41
41
41
39
41
41
41
39
41
41
95
95
96
96
97
PS025113-1212
Register Map