Z8F0830HH020SG Datasheet, PDF (73/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
55
Architecture
Figure 9 displays the Interrupt Controller block diagram.
Port Interrupts
Internal Interrupts
High
Priority
Medium
Priority
Vector
Priority
Mux
IRQ Request
Low
Priority
Figure 9. Interrupt Controller Block Diagram
Operation
This section describes the operational aspects of the following functions.
Master Interrupt Enable: see page 55
Interrupt Vectors and Priority: see page 56
Interrupt Assertion: see page 56
Software Interrupt Assertion: see page 57
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control Register globally enables
and disables the interrupts.
Interrupts are globally enabled by any of the following actions:
• Execution of an EI (enable interrupt) instruction
• Execution of an IRET (return from interrupt) instruction
PS025113-1212
Architecture