Z8F0830HH020SG Datasheet, PDF (35/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
17
Register Map
Table 8 provides an address map of the Z8 Encore! F0830 Series register file. Not all
devices and package styles in the Z8 Encore! F0830 Series support the ADC or all of the
GPIO ports. Consider registers for unimplemented peripherals as reserved.
Table 8. Register File Address Map
Address (Hex) Register Description
General Purpose RAM
000–0FF
General purpose register file RAM
100–EFF
Reserved
Timer 0
F00
F01
F02
Timer 0 high byte
Timer 0 low byte
Timer 0 reload high byte
F03
Timer 0 reload low byte
F04
Timer 0 PWM high byte
F05
Timer 0 PWM low byte
F06
Timer 0 control 0
F07
Timer 0 control 1
Timer 1
F08
F09
F0A
F0B
Timer 1 high byte
Timer 1 low byte
Timer 1 reload high byte
Timer 1 reload low byte
F0C
Timer 1 PWM high byte
F0D
Timer 1 PWM low byte
F0E
Timer 1 control 0
F0F
Timer 1 control 1
F10–F6F
Reserved
Analog-to-Digital Converter (ADC)
F70
ADC control 0
F71
Reserved
F72
ADC data high byte
Note: XX = Undefined.
Mnemonic Reset (Hex) Page No.
—
XX
—
XX
T0H
00
83
T0L
01
83
T0RH
FF
85
T0RL
FF
85
T0PWMH
00
86
T0PWML
00
86
T0CTL0
00
87
T0CTL1
00
88
T1H
00
83
T1L
01
83
T1RH
FF
85
T1RL
FF
85
T1PWMH
00
86
T1PWML
00
86
T1CTL0
00
87
T1CTL1
00
83
—
XX
ADCCTL0
00
102
—
XX
ADCD_H
XX
103
PS025113-1212
Register Map