Z8F0830HH020SG Datasheet, PDF (122/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
104
Sample Settling Time Register
The Sample Settling Time Register, shown in Table 66, is used to program a delay after
the SAMPLE/HOLD signal is asserted and before the START signal is asserted; an ADC
conversion then begins. The number of clock cycles required for settling will vary from
system to system depending on the system clock period used. The system designer should
program this register to contain the number of clocks required to meet a 0.5 µs minimum
settling time.
Table 66. Sample Settling Time (ADCSST)
Bit
7
6
5
4
3
2
1
0
Field
Reserved
SST
RESET
0
1
1
1
1
R/W
R
R/W
Address
F74H
Bit
[7:4]
[3:0]
SST
Description
Reserved
These bits are reserved and must be programmed to 0000.
0h–Fh = Sample settling time in number of system clock periods to meet 0.5 µs minimum.
PS025113-1212
ADC Control Register Definitions