Z8F0830HH020SG Datasheet, PDF (123/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
105
Sample Time Register
The Sample Time Register, shown in Table 67, is used to program the length of active time
for a sample after a conversion has begun by setting the START bit in the ADC Control
Register. The number of system clock cycles required for the sample time varies from sys-
tem to system, depending on the clock period used. The system designer should program
this register to contain the number of system clocks required to meet a 1 µs minimum sam-
ple time.
Table 67. Sample Time (ADCST)
Bit
7
6
5
4
3
2
1
0
Field
Reserved
ST
RESET
0
1
1
1
1
1
1
R/W
R/W
R/W
Address
F75H
Bit
[7:6]
[5:0]
ST
Description
Reserved
These bits are reserved and must be programmed to 00.
0h–Fh = Sample-hold time in number of system clock periods to meet 1 µs minimum.
PS025113-1212
ADC Control Register Definitions