Z8F0830HH020SG Datasheet, PDF (111/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
93
Watchdog Timer Refresh
Upon first enable, the Watchdog Timer is loaded with the value in the Watchdog Timer
Reload registers. The Watchdog Timer counts down to 000000H unless a WDT instruc-
tion is executed by the eZ8 CPU. Execution of the WDT instruction causes the downcoun-
ter to be reloaded with the WDT reload value stored in the Watchdog Timer Reload
registers. Counting resumes following the Reload operation.
When the Z8 Encore! F0830 Series devices are operating in DEBUG Mode (using the On-
Chip Debugger), the Watchdog Timer must be continuously refreshed to prevent any
WDT time-outs.
Watchdog Timer Time-Out Response
The Watchdog Timer times out when the counter reaches 000000H. A time-out of the
Watchdog Timer generates either an interrupt or a system reset. The WDT_RES Flash
option bit determines the time-out response of the Watchdog Timer. See the Flash Option
Bits chapter on page 124 for information about programming the WDT_RES Flash option
bit.
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the Watchdog Timer issues
an interrupt request to the Interrupt Controller and sets the WDT status bit in the Reset
Status Register. If interrupts are enabled, the eZ8 CPU responds to the interrupt request by
fetching the Watchdog Timer interrupt vector and executing code from the vector address.
After time-out and interrupt generation, the Watchdog Timer counter resets to its maxi-
mum value of FFFFFH and continues counting. The Watchdog Timer counter will not
automatically return to its reload value.
The Reset Status Register (see Table 12 on page 29) must be read before clearing the
WDT interrupt. This read clears the WDT time-out flag and prevents further WDT inter-
rupts occurring immediately.
WDT Interrupt in STOP Mode
If configured to generate an interrupt when a time-out occurs and the Z8 Encore! F0830
Series devices are in STOP Mode, the Watchdog Timer automatically initiates a Stop
Mode Recovery and generates an interrupt request. Both the WDT status bit and the STOP
bit in the Watchdog Timer Control Register are set to 1 following a WDT time-out in
STOP Mode. See the Reset and Stop Mode Recovery chapter on page 21 for more infor-
mation about Stop Mode Recovery operations.
If interrupts are enabled, following completion of the Stop Mode Recovery, the eZ8 CPU
responds to the interrupt request by fetching the Watchdog Timer interrupt vector and exe-
cutes the code from the vector address.
PS025113-1212
Operation