Z8F0830HH020SG Datasheet, PDF (114/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
96
Watchdog Timer Reload Upper, High and Low Byte Registers
The Watchdog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) regis-
ters, shown in Tables 60 through 62, form the 24-bit reload value that is loaded into the
Watchdog Timer when a WDT instruction executes. This 24-bit value ranges across bits
[23:0] to encompass the three bytes {WDTU[7:0], WDTH[7:0], WDTL[7:0]}. Writing to
these registers sets the appropriate reload value; reading from these registers returns the
current Watchdog Timer count value.
Caution: The 24-bit WDT reload value must not be set to a value less than 000004H.
Table 60. Watchdog Timer Reload Upper Byte Register (WDTU)
Bit
7
6
5
4
3
2
1
Field
WDTU
RESET
0
0
0
0
0
0
0
R/W
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Address
FF1H
Note: *A read returns the current WDT count value; a write sets the appropriate reload value.
Bit
[7:0]
WDTU
Description
WDT Reload Upper Byte
Most significant byte (MSB), Bits[23:16], of the 24-bit WDT reload value.
0
0
R/W*
Table 61. Watchdog Timer Reload High Byte Register (WDTH)
Bit
7
6
5
4
3
2
1
Field
WDTH
RESET
0
0
0
0
0
1
0
R/W
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Address
FF2H
Note: *A read returns the current WDT count value; a write sets the appropriate reload value.
Bit
[7:0]
WDTH
Description
WDT Reload High Byte
Middle byte, bits[15:8] of the 24-bit WDT reload value.
0
0
R/W*
PS025113-1212
Watchdog Timer Control Register Definitions