Z8F0830HH020SG Datasheet, PDF (74/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
56
• Writing 1 to the IRQE bit in the Interrupt Control Register
Interrupts are globally disabled by any of the following actions:
• Execution of a DI (disable interrupt) instruction
• eZ8 CPU acknowledgement of an interrupt service request from the Interrupt Control-
ler
• Writing a 0 to the IRQE bit in the Interrupt Control Register
• Reset
• Execution of a trap instruction
• Illegal instruction Trap
• Primary oscillator fail trap
• Watchdog Oscillator fail trap
Interrupt Vectors and Priority
The Interrupt Controller supports three levels of interrupt priority. Level 3 is the highest
priority, level 2 is the second highest priority and level 1 is the lowest priority. If all of the
interrupts are enabled with identical interrupt priority (all as level 2 interrupts, for exam-
ple), the interrupt priority is assigned from highest to lowest as specified in Table 34 on
page 54. Level 3 interrupts are always assigned higher priority than level 2 interrupts and
level 2 interrupts are assigned higher priority than level 1 interrupts. Within each interrupt
priority level (level 1, level 2 or level 3), priority is assigned as specified in Table 34,
above. Reset, Watchdog Timer interrupt (if enabled), primary oscillator fail trap, Watch-
dog Oscillator fail trap and illegal instruction trap always have highest (level 3) priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period (sin-
gle pulse). When the interrupt request is acknowledged by the eZ8 CPU, the correspond-
ing bit in the interrupt request register is cleared. Writing 0 to the corresponding bit in the
interrupt request register clears the interrupt request.
Caution: Zilog recommends not using a coding style that clears bits in the Interrupt Request reg-
isters. All incoming interrupts received between execution of the first LDX command
and the final LDX command are lost. See Example 1, which follows.
Example 1. A poor coding style that can result in lost interrupt requests:
PS025113-1212
Operation