Z8F0830HH020SG Datasheet, PDF (108/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
90
Bit
[6]
TPOL
(cont’d)
Description (Continued)
PWM DUAL OUTPUT Mode
0 = Timer output is forced Low (0) and timer output complement is forced High (1), when the
timer is disabled. When enabled and the PWM count matches, the timer output is forced
High (1) and forced Low (0) when enabled and reloaded. When enabled and the PWM
count matches, the timer output complement is forced Low (0) and forced High (1) when
enabled and reloaded.
1 = Timer output is forced High (1) and timer output complement is forced Low (0) when the
timer is disabled. When enabled and the PWM count matches, the timer output is forced
Low (0) and forced High (1) when enabled and reloaded.When enabled and the PWM
count matches, the timer output complement is forced High (1) and forced Low (0) when
enabled and reloaded. The PWMD field in the TxCTL0 register determines an optional
added delay on the assertion (Low to High) transition of both timer output and timer output
complement for deadband generation.
CAPTURE RESTART Mode
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
COMPARATOR COUNTER Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled, the timer output signal is complemented on timer reload.
[5:3]
PRES
Caution: When the timer output alternate function TxOUT on a GPIO port pin is enabled,
TxOUT will change to whatever state the TPOL bit is in. The timer does not need to be enabled
for that to happen. Additionally, the port data direction sub register is not needed to be set to
output on TxOUT. Changing the TPOL bit when the timer is enabled and running does not
immediately change the polarity TxOUT.
Prescale Value
The timer input clock is divided by 2^PRES, where PRES can be set from 0 to 7. The prescaler is
reset each time the timer is disabled. This reset ensures proper clock division each time the
timer is restarted.
000 = Divide by 1.
001 = Divide by 2.
010 = Divide by 4.
011 = Divide by 8.
100 = Divide by 16.
101 = Divide by 32.
110 = Divide by 64.
111 = Divide by 128.
PS025113-1212
Timer Control Register Definitions