Z8F0830HH020SG Datasheet, PDF (45/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
27
The eZ8 CPU fetches the reset vector at program memory addresses 0002H and 0003H
and loads that value into the program counter. Program execution begins at the reset vector
address. Following Stop Mode Recovery, the STOP bit in the Reset Status (RSTSTAT)
Register is set to 1. Table 11 lists the Stop Mode Recovery sources and resulting actions.
The following sections provide more details about each of the Stop Mode Recovery
sources.
Table 11. Stop Mode Recovery Sources and Resulting Action
Operating
Mode
STOP Mode
Stop Mode Recovery Source
Action
Watchdog Timer time-out when configured Stop Mode Recovery
for Reset
Watchdog Timer time-out when configured Stop Mode Recovery followed by interrupt
for interrupt
(if interrupts are enabled)
Data transition on any GPIO port pin enabled Stop Mode Recovery
as a Stop Mode Recovery source
Assertion of external RESET Pin
System reset
Debug pin driven Low
System reset
Stop Mode Recovery using WDT Time-Out
If the Watchdog Timer times out during STOP Mode, the device undergoes a Stop Mode
Recovery sequence. In the Reset Status (RSTSTAT) Register, the WDT and STOP bits are
set to 1. If the Watchdog Timer is configured to generate an interrupt upon time-out and
the Z8 Encore! F0830 Series device is configured to respond to interrupts, the eZ8 CPU
services the WDT interrupt request following the normal Stop Mode Recovery sequence.
Stop Mode Recovery using GPIO Port Pin Transition
Each of the GPIO port pins may be configured as a Stop Mode Recovery input source. If
any GPIO pin is enabled as a Stop Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop Mode Recovery. In the Reset Sta-
tus (RSTSTAT) Register, the STOP bit is set to 1.
Caution: In STOP Mode, the GPIO Port Input Data registers (PxIN) are disabled. These Port Input
Data registers record the port transition only if the signal stays on the port pin through the
end of the Stop Mode Recovery delay. As a result, short pulses on the port pin can initiate
Stop Mode Recovery without being written to the Port Input Data Register or without ini-
tiating an interrupt (if enabled for that pin).
PS025113-1212
Stop Mode Recovery