Z8F0830HH020SG Datasheet, PDF (46/257 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore!^® F0830 Series
Product Specification
28
Stop Mode Recovery Using the External RESET Pin
When the Z8 Encore! F0830 Series device is in STOP Mode and the external RESET pin
is driven low, a system reset occurs. Because of a glitch filter operating on the RESET pin,
the low pulse must be greater than the minimum width specified about 12 ns or it is
ignored. The EXT bit in the Reset Status (RSTSTAT) Register is set.
Debug Pin Driven Low
Debug reset is initiated when the On-Chip Debugger detects any of the following error
conditions on the DBG pin:
• Serial break (a minimum of nine continuous bits Low)
• Framing error (received STOP bit is Low)
• Transmit collision (simultaneous OCD and host transmission detected by the OCD)
When the Z8F0830 Series device is operating in STOP Mode, the debug reset will cause a
system reset. The On-Chip Debugger block is not reset, but the remainder of the chip’s
operations go through a normal system reset. The POR bit in the Reset Status (RSTSTAT)
Register is set to 1.
Reset Register Definitions
The following sections define the Reset registers.
Reset Status Register
The Reset Status (RSTSTAT) Register, shown in Table 12, is a read-only register that indi-
cates the source of the most recent Reset event, Stop Mode Recovery event or Watchdog
Timer time-out event. Reading this register resets the upper four bits to 0.
This register shares its address with the Watchdog Timer Control Register, which is write-
only.
PS025113-1212
Debug Pin Driven Low